Task inside Interface
interface simple_bus (input logic clk); // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
modport slave(input req, addr, mode, start, clk,
output gnt, rdy,
ref data,
import slaveRead,slaveWrite);
//import into module that uses the modport
modport master(input gnt, rdy, clk,
output req, addr, mode, start,
ref data,
import masterRead,masterWrite);
//import into module that uses the modport
task masterRead(input logic[7:0] raddr=8'h0); // masterRead method
$display("Inside Master_Read");
endtask
task slaveRead;
$display("Inside Slave_Read");
endtask
task masterWrite(input logic [7:0] waddr=8'h0);
$display("Inside Master_Write");
endtask
task slaveWrite;
$display("Inside Slave_Write");
endtask
endinterface: simple_bus
module mod (interface i) ;
always@(posedge i.clk) begin
i.slaveRead;
i.masterRead;
i.slaveWrite;
i.masterWrite;
end
endmodule
module top;
logic clk = 0;
simple_bus sb_intf(clk); // Instantiate the interface
mod m (sb_intf.master) ;
always #5 clk=!clk;
initial begin
#50 $finish;
end
endmodule
interface simple_bus (input logic clk); // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
modport slave(input req, addr, mode, start, clk,
output gnt, rdy,
ref data,
import slaveRead,slaveWrite);
//import into module that uses the modport
modport master(input gnt, rdy, clk,
output req, addr, mode, start,
ref data,
import masterRead,masterWrite);
//import into module that uses the modport
task masterRead(input logic[7:0] raddr=8'h0); // masterRead method
$display("Inside Master_Read");
endtask
task slaveRead;
$display("Inside Slave_Read");
endtask
task masterWrite(input logic [7:0] waddr=8'h0);
$display("Inside Master_Write");
endtask
task slaveWrite;
$display("Inside Slave_Write");
endtask
endinterface: simple_bus
module mod (interface i) ;
always@(posedge i.clk) begin
i.slaveRead;
i.masterRead;
i.slaveWrite;
i.masterWrite;
end
endmodule
module top;
logic clk = 0;
simple_bus sb_intf(clk); // Instantiate the interface
mod m (sb_intf.master) ;
always #5 clk=!clk;
initial begin
#50 $finish;
end
endmodule